Exploring the Design Space of DRAM Caches
نویسندگان
چکیده
Die-stacked DRAM caches represent an emerging technology that offers a new level of cache between SRAM caches and main memory. As compared to SRAM, DRAM caches offer high capacity and bandwidth but incur high access latency costs. Therefore, DRAM caches face new design considerations that include the placement and granularity of tag storage in either DRAM or SRAM. The associativity of the cache and the inherent behavior and constraints of DRAM are also factors to consider in the design of DRAM caches. In this thesis, we explore and analyze the different factors of DRAM cache design and their impact upon performance; the goal is to identify promising areas of the design space that deserve further study.
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